This invention relates to methods of forming integrated circuitry, to methods of forming a capacitor, to methods of forming DRAM integrated circuitry, to integrated circuitry and to DRAM integrated circuitry.
As DRAMs increase in memory cell density, there is a continuing challenge to maintain sufficiently high storage capacitance despite decreasing cell area. Additionally, there is a continuing goal to further decrease cell area. One principal way of increasing cell capacitance is through cell structure techniques. Such techniques include three-dimensional cell capacitors, such as trenched or stacked capacitors. Yet as feature size continues to become smaller and smaller, development of improved materials for cell dielectrics as well as the cell structure are important. The feature size of 256 Mb DRAMs and beyond will be on the order of 0.25 micron or less, and conventional dielectrics such as SiO2 and Si3N4 might not be suitable because of small dielectric constants.
Highly integrated memory devices, such as 256 Mbit DRAMs and beyond, are expected to require a very thin dielectric film for the 3-dimensional capacitor of cylindrically stacked or trench structures. To meet this requirement, the capacitor dielectric film thickness will be below 2.5 nm of SiO2 equivalent thickness. Insulating inorganic metal oxide materials, such as Ta2O5 and barium strontium titanate, have high dielectric constants and low leakage current which make them attractive as cell dielectric materials for high density DRAMs and non-volatile memories. All of these materials incorporate oxygen and are otherwise exposed to oxygen and anneal for densification to produce the desired capacitor dielectric layer. In many of such applications, it will be highly desirable to utilize metal for the capacitor electrodes, thus forming a metal-insulator-metal capacitor.
DRAM and other circuitry having devices using high dielectric constant dielectric materials are expected to be sensitive to high temperature processing in hydrogen containing ambients. Presently, most all integrated circuitry fabrication includes a final hydrogen atmosphere anneal to facilitate one or more of aluminum alloying, of threshold voltage (Vt) adjustment, of junction leakage stabilization and of dangling bond repair in the typical bulk monocrystalline silicon substrate. Hydrogen is a very diffusive material, typically diffusing into and through the overlying layers to the bulk substrate during the high temperature hydrogen anneal. Unfortunately, hydrogen remaining in high dielectric constant capacitor dielectrics has a significant adverse effect on current leakage in the capacitor, potentially leading to complete failure of the capacitor and corresponding destruction of the DRAM cell.
Overcoming such problem in DRAM circuitry fabrication was a motivation for the invention, but the invention is in no way so limited.
The invention comprises a method of forming integrated circuitry, a method of forming a capacitor, a methods of forming DRAM integrated circuitry, integrated circuitry and DRAM integrated circuitry. In but one implementation, a method of forming integrated circuitry includes forming a first capacitor electrode layer over a substrate. A capacitor dielectric layer is formed over the first capacitor electrode layer. A second capacitor electrode layer is formed over the capacitor dielectric layer and a capacitor is formed comprising the first capacitor electrode layer, the capacitor dielectric layer and the second capacitor electrode layer. A silicon nitride comprising layer is physical vapor deposited over the second capacitor electrode layer. A final passivation layer is formed over the physical vapor deposited silicon nitride comprising layer.
In one implementation, integrated circuitry includes a first capacitor electrode layer received over a substrate. A capacitor dielectric layer is received over the first capacitor electrode layer. A second capacitor electrode layer is received over the capacitor dielectric layer. The first capacitor electrode layer, the capacitor dielectric layer and the second capacitor electrode layer comprise a capacitor. A silicon nitride comprising layer is received over the second capacitor electrode layer. At least a portion of the silicon nitride comprising layer contacts at least a portion of the second capacitor electrode layer.
Other aspects and implementations are disclosed or contemplated.